1. Field of the Invention
The present invention relates to a nonvolatile memory device and, more particularly, to a flat-cell mask ROM that prevents the deterioration of cell uniformity attributed to the spacing between word and select lines.
2. Description of the Related Art
Semiconductor memory devices are primarily divided into random access memories (RAMs) and read only memories (ROMs). RAMs lose data over time while ROMs do not. Examples of RAM devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Examples of ROM devices include mask ROMs.
Mask ROMs have characteristic cell structures primarily classified into NOR and NAND types. Preexisting NOR-type cells are easy to operate at high speeds by virtue of their high cell currents. NOR-type cells, however, have a significant disadvantage in that they have a large cell area. In contrast, NAND-type cells have low cell current and have a small cell area, thus, they improve semiconductor integration. Accordingly, NAND-type cell structures are preferred over NOR-type cells.
NOR-type flat-cells can be made to have small cell areas like NAND-type cells while keeping the advantages of the NOR-type cells. As is well known, the NOR-type flat-cells are free of the field oxide used for element isolation in the cell array. NOR-type flat-cells use high cell currents and have improved cell uniformity over NAND-type cells so that they can be operated at high speeds with low voltages. In addition, NOR-type flat-cells make it easy to develop multi-bit cells (MBC) or multi-level cells (MLC) for storing a plurality of information in a single cell.
FIGS. 1 and 2 refer to a NOR-type flat-cell mask ROM. FIG. 1 is a schematic plan view showing the NOR-type flat-cell mask ROM disclosed in Korean Patent Application No. 97-20507 and FIG. 2 is an equivalent circuit diagram of the cells shown in FIG. 1. The NOR-type flat-cells have a cell structure that lowers the channel resistance in a read-out path and reduces the number of select lines.
As shown in FIGS. 1 and 2, the NOR-type flat-cell mask ROM has a matrix structure in which a plurality of burial N+ diffusion layers 12 extend in the column direction. The plurality of burial N+ diffusion layers 12 form the source/drains and the sub bit-lines of the cell transistors on the surface of the semiconductor device. A plurality of word lines W/L1-W/Ln is laid overlapping with and extending perpendicularly to the burial N+ diffusion layers. Each word line W/L1-W/Ln is the gate electrode of a cell transistor. A plurality of metal lines B/L1, B/L2, . . . is arranged parallel to the burial N+ diffusion layers 12. The metal lines B/L1, B/L2, . . . are alternatively arranged as main bit-lines and ground lines.
In order to operate the cells of the NOR-type flat-cell mask ROM, a predetermined voltage level between 0-3.3V is applied to selected bit lines. Additionally, zero volts is applied to adjacent ground lines. Depending on the combination of the select lines S/L1, S/L2, S/L3, S/L4, a first, a second, a third, and a fourth column are correspondingly selected. In the equivalent circuit diagram of FIG. 2, for instance, if a memory cell array of the first column is selected, a predetermined voltage is applied to the first bit line B/L1 while zero volts are applied to the second bit line B/L2. At this time, the first and the third select lines S/L1 and S/L3 are in a high voltage state and the second and the fourth select lines S/L2 and S/L4 are in a low voltage state. As a result, the column selection enters a read state in which the word lines W/L1, W/L2, . . . W/Lnxe2x88x921, W/Ln of the memory cell array in the first column are ready to be read. For raw selection, applying a high voltage to the selected word lines and zero voltage to the non-selected word lines begins the read operation.
Where the threshold voltage Vth of the cell transistors is lower than the voltage of the selected word lines, the selected cells are turned-on and the discharge path from the bit lines to the ground lines is detected, thereby reading the cells as being xe2x80x9cONxe2x80x9d. On the other hand, where the threshold voltage Vth of the cell transistors is higher than the voltage of the selected word lines, the selected cells are turned-off to maintain the voltage of the bit lines, thereby reading the cells as being xe2x80x9cOFFxe2x80x9d.
The NOR-type flat-cell mask ROM requires that the word lines and select lines in the memory cell array should be spaced a predetermined distance. This is a minimal necessary condition to achieve stability in the electrical connection from the main bit-lines through the select lines to the sub bit-lines (burial N+ diffusion layers 12) of the memory cell array. That is, a predetermined space between a word line and a select line is needed to prevent violation of the element isolation and minimum design rules. The spacing between word line and select line, however, is a negative factor against cell uniformity and design rule reduction. For example, the first word line W/L1 and the nth word line W/Ln, each lying adjacent to a select line at a predetermined distance, show a different critical dimension CD as compared with the word lines repeated within the memory cell array. This situation can be explained by the so-called loading effect. The loading effect is caused by a number of processes including the photograph and dry etching processes used for patterning word lines.
In the photograph process for forming the patterns repeated under a minimum design-rule, over-exposing is carried out with the aim of avoiding the problems derived from resolution limit. In this case, the loose patterns, which are free from the minimum design-rule, however, show a large skew deviation of the dimension CD. In particular, where the exposure process is carried out on the basis of the space among the repeated word lines W/L2, . . . , W/Lnxe2x88x921, the first and the nth word lines W/L1 and W/Ln are exposed at a greater energy than the standard energy because the space between the second select line S/L2 and the first word line W/L1 or between the third select line S/L3 and the nth word line W/Ln is large. Accordingly, the first and nth word lines W/L1, W/Ln come to have different dimensions CD than the repeated word lines W/L2, . . . , W/Lnxe2x88x921. This variation in dimension CD appears in the dry etch process as well. When a dry etch process is executed in a pattern-dense area and a pattern-sparse area, the evaporation pressure caused by the reaction between the etchant in a plasma state and the area to be etched is significantly reduced in the pattern-dense area, resulting in deterioration of etch uniformity. Accordingly, the skew deviation of dimension CD becomes large at the first and nth word lines W/L1 and W/Ln.
A fabricating method for NOR-type flat-cells comprises forming a burial N+ diffusion layer which is provided as a sub bit-line on a Pxe2x88x92 substrate surface within a memory cell array, forming a gate dielectric and a gate electrode (word line), implanting Nxe2x88x92source/drain ions for a LDD (lightly doped drain) structure, forming a sidewall spacer, and implanting N+ source/drain ions into a peripheral circuit region. As select lines and word lines are spaced at predetermined distances, the junction boundary between the burial N+ diffusion layer and the Pxe2x88x92 substrate is clearly exposed. Thus, when a whole surface etch-back process is carried out to form the sidewall spacer, over-etching is made to the exposed surface, deteriorating the junction breakdown voltage.
In addition, during a programming process, impurities are implanted in a channel of a cell transistor to selectively shift threshold voltages. When programming is carried out after the formation of word lines, the spacing of the select lines from the word lines degrades the uniformity of threshold voltage. Moreover, where the programming process is applied as an after contact programming (ACP) process, when a planarization layer is formed by reflowing a BPSG film, it flows into the spacing between the select lines and the word lines, so that the BPSG film is thinner over the first and nth word lines W/L1 and W/Ln than over others. This results in degrading program uniformity when the programming process is carried out after planarization of the BPSG film.
Accordingly, an object of the present invention is to overcome the disadvantages associated with prior art, nonvolatile memory devices.
Another object of the present invention is to provide a nonvolatile memory device that prevents deterioration of cell uniformity attributable to the spacing between word and select lines.
A nonvolatile memory device is provided. The nonvolatile memory device includes a plurality of burial N+ diffusion layers formed over a semiconductor substrate, each burial N+ diffusion layer being a source/drain of a cell transistor and a sub bit-line of a memory cell array and a plurality of word lines formed over the semiconductor substrate with a plurality of gate dielectrics interposed therebetween, the plurality of word lines extending perpendicularly to the plurality of burial N+ diffusion layers. A plurality of select lines extending parallel to the word lines for selectively transferring external electrical signals via main bit-lines to the sub bit-lines, the main bit-lines extending parallel to the sub bit-lines. A plurality of dummy lines extending parallel to the plurality of word lines, each dummy line being formed between a selected word line and an adjacent select line.
The plurality of dummy lines receive a constant voltage when the cell transistor is in an operative state. The constant voltage is a ground voltage.
Adjacent dummy lines are separated by a dummy line pitch and adjacent word lines are separated by a word line pitch, the dummy line pitch being substantially equal to the word line pitch. Furthermore, the plurality of dummy lines is formed of a same material as the plurality of word lines. The selected word line and the adjacent select line are spaced apart between 0.1-1.5 xcexcm.
A method for making a nonvolatile memory device on a semiconductor substrate is also provided. The method includes forming a plurality of N+ burial diffusion layers on the substrate and forming a plurality of word lines perpendicular to the plurality of N+ burial diffusion layers. The method further includes forming a plurality of select lines parallel to the plurality of word lines and forming a plurality of dummy lines parallel to the plurality of word lines, each dummy line arranged between a selected word line and an adjacent select line.